RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 70

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

3.0 Registers
3.3 Register Description
lfsr_lock
htur_lfsr
descr_on
A 4-bit read/write register interpreted as an unsigned binary number. Specifies a number of additional symbol
delays inserted in the peak detector input path of the symbol detector. Must be set to a value that equalizes the
total path delay in each of the peak detector and slicer input paths according to the following formula: peak
detector delay register value = DAGC delays + FFE delays – fixed peak detector input delays. The DAGC and
FFE delays are not fixed, but result from the microprogrammed implementation of these functions. The value
should be set according to software supplied by Conexant.
3-24
0x3B—Peak Detector Delay Register (peak_detector_delay)
—
7
LFSR Lock—Read/write control bit that enables the auto-scrambler synchronization mode
(lfsr_lock) in the detector when set and disables this mode when cleared. Affects the behavior
of the scrambler/descrambler function, overriding the descr_on setting. When enabled, the
scrambler/descrambler is forced into the descrambler mode for 23 cycles. It is then switched to
the scrambled-1s mode for 128 cycles. While in this mode, the outputs of the scrambler and the
slicer/peak detector are compared against one another. The number of equivalent bits (equal
comparisons) is accumulated and compared to the value of the Scrambler Synchronization
Threshold Register [scr_sync_th; 0x2E].
interrupt flag is set in the IRQ source register [irq_source; 0x05] and the process terminates
with the scrambler/descrambler left in the scrambled-1s mode. (The sync interrupt flag cannot
be cleared while lfsr_lock remains high.) After 128 cycles, if the threshold is not exceeded, the
accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for another
23 cycles, and the process repeats until either sync is achieved or this mode is disabled. Once
disabled, the sync interrupt flag can be cleared (if active) and the scrambler/descrambler
returns to the mode specified by descr_on.
Remote Unit (HTU-R/NT) Polynomial Select—Read/write control bit that selects one of two
feedback polynomials for the scrambler/descrambler. When set, this bit selects the remote unit
(HTU-R/NT) receive polynomial (x
(HTU-C/LT) polynomial (x
Descrambler/Scrambler Select—Read/write control bit that configures the
scrambler/descrambler function as a descrambler when set, and as a scrambler when cleared.
As a scrambler, this bit enables the scrambler/descrambler to generate a scrambled-all-1s
sequence (constant high logic-level input); all incoming data is ignored. In the auto-scrambler
synchronization mode (lfsr_lock = 1), this selection is overwritten though the value of the
control bit is unaffected.
—
At any time during the 128 cycles, if the count exceeds the threshold (greater than), the sync
6
—
5
Preliminary Information
– 23
—
4
+ x
Conexant
– 18
– 23
+ 1).
+ x
– 5
D[3]
3
+ 1); when cleared, it selects the local unit
D[2]
Single-Chip SDSL/HDSL Transceiver
2
D[1]
1
N8973DSD
RS8973
D[0]
0