RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 46

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.6 Test and Diagnostic Interface (JTAG)
Table 2-7. JTAG Device Identification Register
2-22
0
NOTE(S):
(1) Consult factory for current version number.
Version
4 bits
0
0x0
0
(1)
0
0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 1
2.6 Test and Diagnostic Interface (JTAG)
To access individual chips for PCB verification, special circuitry is incorporated
within the transceiver, which complies with IEEE Std 1149.1-1990, Standard Test
Access Port and Boundary Scan Architecture set by the Joint Test Action Group
(JTAG).
printed circuit board can be achieved through these four TAP pins.
pin, both inputs and outputs. All scan cells are interconnected in a boundary-scan
register which applies or captures test data used for functional verification of the
PC board interconnection. JTAG is particularly useful for board testers using
functional testing methods.
capture the respective logic levels. Since all of the digital pins are interconnected
as a long shift register, the TAP logic has access and control of all necessary pins
to verify connectivity. For mixed signal ICs, the chip boundary definition is
expanded to include the on-chip interface between digital and analog circuitry.
During a power-up sequence, internal supply-monitor circuitry ensures that each
pin is initialized to operate as a 2B1Q transceiver, instead of JTAG test mode.
register is included and contains a revision number, a part number, and a
manufacturer’s identification code specific to Conexant (see
this register is through the TAP controller through a standard JTAG instruction.
controller. Board connectivity can be verified at all digital pins through a set of
two instructions accessible through the use of a state machine, standard to all
JTAG controllers. Refer to the IEEE Std 1149.1 specification for details
concerning the Instruction Register and JTAG state machine. A Boundary Scan
Description Language (BSDL) file for the RS8973 is also available from the
factory upon request.
0x230D (RS8973)
Part Number
JTAG has four dedicated pins that comprise the test access port (TAP):
1.
2.
3.
4.
Verification of the integrated circuit’s connection to other modules on the
JTAG’s approach to testability uses boundary scan cells placed at each digital
The boundary-scan cells at each digital pin provide the ability to apply and
The JTAG standard defines an optional device identification register. This
A variety of verification procedures can be performed through the TAP
16 bits
Test Mode Select (TMS)
Test Clock (TCK)
Test Data Input (TDI)
Test Data Out (TDO)
Preliminary Information
Conexant
Single-Chip SDSL/HDSL Transceiver
Manufacturer ID
11 bits
0x0D6
Table
2-7). Access to
1
N8973DSD
0
RS8973
1
TDO