RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 78

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

3.0 Registers
3.3 Register Description
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimal.
When written, this register causes the selected 16-bit location of the equalizer register file to be subsequently
loaded into the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within
2 symbol periods. Does not affect the value of the register file location. An address map of the shared register
file, as defined by the factory-delivered microcode, is displayed in
between the time the Read Tap Select Register is written and the time the Access Data Register is read, or the
data may be corrupted.
Table 3-2. Address Map of Shared Register Fill
3-32
0x78—Equalizer Read Select Register (eq_add_read)
—
7
Decimal
16–20
21–25
35–47
8–15
0–7
26
27
28
29
30
31
32
33
34
—
6
D[5:0]
00 0000–00 0111
00 1000–00 1111
01 0000–01 0100
01 0101–01 1001
10 0011–10 1111
D[5]
5
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111
10 0000
10 0001
10 0010
Binary
Preliminary Information
D[4]
4
Conexant
FFE Coefficients 0–7
FFE Data Taps 0–7
EP Coefficients 0–4
EP Data Taps 0–4
DAGC Gain—Least-Significant Word
DAGC Gain—Most-Significant Word
DAGC Output
FFE Output
DAGC Input
FFE Output, Delayed 1 Symbol Period
DAGC Error Signal
Equalizer Error Signal
Slicer Error Signal
Reserved
D[3]
3
Table
3-2. No other data access should occur
Stored Parameter
D[2]
Single-Chip SDSL/HDSL Transceiver
2
D[1]
1
N8973DSD
RS8973
D[0]
0