RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 47

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

N8973DSD
3.0 Registers
3.1 Conventions
Unless otherwise noted, the following conventions apply to all applicable register
descriptions:
• For storage of multiple-bit data fields within a single byte-wide register,
• If only a single data field is stored in a byte-wide register, the field is
• For storage of multiple-byte data words across multiple byte-wide
• When writing to any control or data register with less than all 8-bit
• When reading from any control/status or data register with less than all
• Register values are not affected by RST pin assertion, except for the mode
• The initial values of all registers and RAM are undefined after power is
• The register and bit mnemonics used here are based on the mnemonics
• Writing to unspecified registers may cause unpredictable behavior.
the LSBs of the field are located at the lower register-bit positions, whereas
the MSBs are located at the higher positions.
justified so that the LSB of the field is located in the lowest register-bit
position, bit 0.
registers, the LSBs of the word are located at the lower byte-address
locations, while the MSBs are located at the higher byte-address locations.
positions defined, a logical 0 value must be assigned to each
unused/undefined/reserved position. Writing a logical 1 value to any of
these positions may cause undefined behavior.
8-bit positions defined, an indeterminate value is returned from each
unused/undefined/reserved position.
bit of the Global Modes and Status Register [global_modes; 0x00], the
hclk_freq[1,0] field of the Serial Monitor Source Select Register
[serial_monitor_source; 0x01] and the clk_freq[1,0] field of the PLL
Modes Register [pll_modes; 0x22]. After RST pin assertion, all device
parameters should be reinitialized.
applied. Exceptions include the mode bit of the Global Modes and Status
Register, the hclk_freq[1,0] field of the Serial Monitor Source Select
Register, the clk_freq[9,8] field of PLL Modes Register, and the Clock
Frequency Select Register. In addition, the JTAG state is reset when power
is applied.
used in the Conexant bit pump software.
Preliminary Information
Conexant
3
3-1