RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 5

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
3.0
3.0
N8973DSD
Registers
3.1
Registers
3.2
3.3
Conventions
Register Summary
Register Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
0x00—Global Modes and Status Register (global_modes)
0x01—Serial Monitor Source Select Register (serial_monitor_source)
0x02—Interrupt Mask Register Low (mask_low_reg)
0x03—Interrupt Mask Register High (mask_high_reg)
0x04—Timer Source Register (timer_source)
0x05—IRQ Source Register (irq_source)
0x06—Channel Unit Interface Modes Register (cu_interface_modes)
0x07—Receive Phase Select Register (receive_phase_select)
0x08—Linear Echo Canceller Modes Register (linear_ec_modes)
0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes)
0x0A—Decision Feedback Equalizer Modes Register (dfe_modes)
0x0B—Transmitter Modes Register (transmitter_modes)
0x0C—Timer Restart Register (timer_restart)
0x0D—Timer Enable Register (timer_enable)
0x0E—Timer Continuous Mode Register (timer_continuous)
0x0F—Miscellaneous/Test Register (misc_test)
0x10, 0x11—Startup Timer 1 Interval Register (sut1_low, sut1_high)
0x12, 0x13—Startup Timer 2 Interval Register (sut2_low, sut2_high)
0x14, 0x15—Startup Timer 3 Interval Register (sut3_low, sut3_high)
0x16, 0x17—Startup Timer 4 Interval Register (sut4_low, sut4_high)
0x18, 0x19—Meter Timer Interval Register (meter_low, meter_high)
0x1A, 0x1B—SNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high)
0x1C, 0x1D—General Purpose Timer 3 Interval Register (t3_low, t3_high)
0x1E, 0x1F—General Purpose Timer 4 Interval Register (t4_low, t4_high)
0x20—Clock Frequency Select Register (clock_freq_select)
0x21—ADC Control Register (adc_control)
0x22—PLL Modes Register (pll_modes)
0x23—Test Register (test_reg23)
0x24, 0x25—Timing Recovery PLL Phase Offset Register
(pll_phase_offset_low, pll_phase_offset_high)
0x26, 0x27—Receiver DC Offset Register (dc_offset_low, dc_offset_high)
0x28—Transmitter Calibration Register (tx_calibrate)
0x29—Transmitter Gain Register (tx_gain)
0x2A, 0x2B—Noise-Level Histogram Threshold Register
(noise_histogram_th_low, noise_histogram_th_high)
0x2C, 0x2D—Error Predictor Pause Threshold Register
(ep_pause_th_low, ep_pause_th_high)
0x2E—Scrambler Synchronization Threshold Register (scr_sync_th)
0x30, 0x31—Far-End High Alarm Threshold Register
(far_end_high_alarm_th_low, far_end_high_alarm_th_high)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Preliminary Information
Conexant
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
. . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
. . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
. . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
. . . . . . . . . . . . . . . . . . . . . . . . 3-7
. . . . . . . . . . . . . . . . . . . . . . . 3-14
. . . . . . . . . . . . . . . . . . . . . 3-16
. . . . . . . . . . . . . . . . . . . . . 3-18
. . . . . . . . . . . . . . . . . . . . . 3-22
. . . . . . . . . . . . . . . . . . . . 3-12
. . . . . . . . . . . . . . . . . 3-12
. . . . . . . . . . . . . . . . . 3-13
. . . . . . . . . . . . . . . 3-17
. . . . . . . . . . . . . . . 3-8
. . . . . . . . . . . . . . 3-11
. . . . . . . . . . . . . . 3-16
. . . . . . . . . . . . . . 3-16
. . . . . . . . . . . . . . 3-17
. . . . . . . . . . . . . . 3-17
. . . . . . . . . . . . . . 3-22
. . . . . . . . . . . . 3-13
. . . . . . . . . . . 3-17
. . . . . . . . . . 3-17
. . . . . . . . . . 3-20
Table of Contents
. . . . 3-17
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