PM7311 pmc-sierra, PM7311 Datasheet - Page 119

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x04C: SBI ADD BUS Master Configuration
CLK_MSTR
Reserved
SBI_MODE:
DEFAULT_DRV
This register configures the operation of the SBI ADD BUS.
The CLK_MSTR bit is used to specify whether the Insert block functions as a clock master or
a clock slave. When this bit is a ‘1’ the Insert block is a clock master. When set high, this bit
overrides the individual tributary settings for clock master. The default state of this bit is
clock slave.
The reserved bit must be set to 0 for correct operation of the FREEDM 84A1024L device.
The SBI_MODE bit selects SBI versus SBI336 mode of operation. When set high, 19.44MHz
(SBI bus) is selected. The default state of this bit is 77MHz (SBI336) mode of operation.
The Default Bus Driver selector bit (DEFAULT_DRV) enables the FREEDM 84A1024L to
drive the SBI ADD BUS when no other device is doing so. When set to 1, the INSBI will
drive the bus whenever the ADETECT[1:0] inputs are both 0. When set to 0, the INSBI will
only drive the bus when it has data to send (and when ADETECT[1:0] are both 0). It is
recommended that one device connected to an SBI Bus be nominated as a default driver and
configured to drive the bus when no other device is doing so.
Bit
Bit 31
To
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
DEFAULT_DRV
SBI_MODE
Reserved
CLK_MSTR
Default
X
0
0
0
0
Released
119