PM7311 pmc-sierra, PM7311 Datasheet - Page 141

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x220: RHDL Configuration
This register configures all provisioned receive channels.
TSTD
LENCHK
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred
across the receive APPI. When TSTD is set low, the least significant bit of each byte on the
receive APPI bus (AD[0] and AD[8]) is the first HDLC bit received and the most significant
bit of each byte (AD[7] and AD[15]) is the last HDLC bit received (datacom standard).
When TSTD is set high, AD[0] and AD[8] are the last HDLC bits received and AD[7] and
AD[15] are the first HDLC bits received (telecom standard).
The packet length error check bit (LENCHK) controls the checking of receive packets that
are longer than the maximum programmed length. When LENCHK is set high, receive
packets are aborted and the remainder of the frame discarded when the packet exceeds the
maximum packet length given by MAX[15:0]. When LENCHK is set low, receive packets
are not checked for maximum size and MAX[15:0] must be set to hFFFF.
Note: It is recommended to set this bit to 1. If not set, a string of all 0’s will be
interpreted as an infinite length packet and will cause chunk buffer exhaustion.
Bit
Bit 31
To
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
LENCHK
TSTD
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Default
X
0
0
X
X
X
X
X
X
X
X
Released
141