PM7311 pmc-sierra, PM7311 Datasheet - Page 129

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x10C: RCAS Indirect Channel Provision RAM Timeslot and Control Select
This register provides the link timeslot number and control bits used to access the channel
provision RAM. The RCAS Indirect Channel Provision RAM Link Select register must be valid
before writing this register. Writing to this register triggers an indirect register access.
TSLOT[4:0]
RWB
BUSY
The indirect timeslot number bits (TSLOT[4:0]) indicate the timeslot to be configured or
interrogated in the indirect access. For a channelized T1/J1 link, timeslots 0 to 23 are valid.
For a channelized E1 link, timeslots 0 to 31 are valid. For unchannelized links, only timeslot
0 is valid.
The indirect access control bit (RWB) selects between a configure (write) or interrogate
(read) access to the RCAS channel provision RAM. The address to the channel provision
RAM is constructed by combining the TSLOT[4:0] and LINK number. Writing a logic zero
to RWB triggers an indirect write operation. Data to be written is taken from the PROV, and
the CHAN[9:0] bits of the Indirect Channel Data and Loop back enable register. Writing a
logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as
in an indirect write operation. The data read can be found in the PROV, and the CHAN[9:0]
bits of the RCAS Indirect Channel Data register.
The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set
high when this register is written, to trigger an indirect access, and will stay high until the
access is complete. At which point, BUSY will be set low. This register should be polled to
determine when data from an indirect read operation is available in the RCAS Indirect Data
register or to determine when a new indirect write operation may commence.
Bit
Bit 31
To
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
BUSY
RWB
TSLOT[4]
TSLOT[3]
TSLOT[2]
TSLOT[1]
TSLOT[0]
Default
X
0
0
0
0
0
0
0
Released
129