PM7311 pmc-sierra, PM7311 Datasheet - Page 212

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x918 RS_DRAMC Status and Control Register
This register provides status information regarding the state of the RS_DRAMC. Only one of
SDRAM_INIT, PROV_MODE or FUNC_MODE at any given time is allowed to be set “high” in
this register. Unpredicted behavior may result otherwise. The ECC_OFF bit should be set to 1
prior to or at the same time FPP_INIT is set to 1 for hardware initialization of the FPP_FIFO. For
microprocessor initialization, these bits should be set to 1 prior to the initialization process.
SDRAM _INIT
PROV_MODE
FPP_INIT
Indicates that the initialization sequence of the Resequencing Buffer SDRAMs is in progress.
Since this sequence is executing immediately following power-up, this bit is set to “1” by
default. This bit is automatically cleared when the SDRAM initialization procedure is
completed.
This bit is automatically set by the RS_DRAMC when it finishes executing the initialization
sequence required by the SDRAMs. When set, this bit indicates that the RS_DRAMC is in
“Provision” mode and only the microprocessor can perform memory transactions. This bit
should be cleared by the microprocessor when all SDRAM transactions are complete. In
addition, note that setting this bit while the RS_DRAMC is in “Functional Mode” (with
FUNC_MODE set) will cause undetermined results.
When set, this bit indicates that the RS_DRAMC is in the process of initializing the Free Pool
Pointer (FPP) FIFO used by the resequencing logic (realized in the Resequencing Buffer).
Two options exist for initializing the FPP FIFO: The first requires the microprocessor to set
the FPP_INIT bit. This will prompt a RS_DRAMC based initialization procedure of the
FIFO. The other method is to initialize the FPP FIFO by direct microprocessor accesses. In
that case there is no need to set this bit.
Bit
Bit 31
To
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
—
R/W
R/W
R/W
R/W
R/W
R/W
R
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
Reserved
DECC
ECC_OFF
FUNC_MODE
FPP_INIT
PROV_MODE
SDRAM_INIT
Default
X
0
0
0
0
0
1
0
Released
212