PM7311 pmc-sierra, PM7311 Datasheet - Page 135

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x204: RHDL Indirect Channel Data Register #1
This register contains data read from the channel provision RAM after an indirect read operation
or data to be inserted into the channel provision RAM in an indirect write operation.
* These registers are also readable if no traffic is enabled in the device.
FPTR[11:0]
TAVAIL
The indirect FIFO block pointer (FPTR[11:0]) identifies one of the blocks of the circular
linked list in the partial packet buffer used in the logical FIFO of the current channel. The
FIFO pointer to be written to the channel provision RAM, in an indirect write operation, must
be set up in this register before triggering the write. The FIFO pointer value can be any one
of the blocks provisioned to form the circular buffer.
The indirect Transaction Available bit (TAVAIL) indicates whether the FIFO for the channel
currently contains at least one transaction, defined as either a complete packet or a transaction
sized number of blocks, available for transfer over the receive DMA interface. When TAVAIL
is a logic 1, a transaction is available for transfer. When TAVAIL is a logic 0, a transaction is
not available. TAVAIL is a read-only bit.
Bit
Bit 31
To
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
W*
R/W
W*
R
W
W
W
W
W
W
W
W
W
W
W
W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
PROV
STRIP
Reserved
TAVAIL
FPTR[11]
FPTR[10]
FPTR[9]
FPTR[8]
FPTR[7]
FPTR[6]
FPTR[5]
FPTR[4]
FPTR[3]
FPTR[2]
FPTR[1]
FPTR[0]
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
135