PM7311 pmc-sierra, PM7311 Datasheet - Page 90

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.9.13
Transmit HDLC Processor (THDL-12)
The HDLC processor is a time-slice state machine that can process up to 1024 independent
HDLC channels. The state vector and provisioning information for each HDLC channel is stored
in a RAM. Whenever the TCAS-12 requests data, the appropriate state vector is read from the
RAM, processed and finally written back to the RAM. The HDLC state-machine can be
configured to perform flag insertion, bit stuffing and CRC generation. The HDLC processor
requests data from the partial packet processor whenever a request for HDLC channel data
arrives. However, the HDLC processor does not start transmitting a packet until the entire packet
is stored in the HDLC channel FIFO or until the FIFO free space is less than the software
programmable limit. If an HDLC channel FIFO under-runs, the HDLC processor aborts the
packet, and generates an interrupt.
The configuration of the HDLC processor is accessed using indirect channel read and write
operations. When an indirect operation is performed, the information is accessed from RAM
during a null clock cycle inserted by the TCAS-12 block. Writing new provisioning data to an
HDLC channel resets the channel’s entire state vector.
Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 64 Kbyte partial packet RAM, which is divided
into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular
HDLC channel FIFO buffers. Thus, non-contiguous sections of RAM can be allocated in the
partial packet buffer RAM to create an HDLC channel FIFO. Figure 34 shows an example of
three blocks (blocks 1, 3, and 200) linked together to form a 48 byte HDLC channel FIFO. The
three pointer values would be written sequentially using indirect block write accesses. When an
HDLC channel is provisioned within this FIFO, the state machine can be initialized to point to
any one of the three blocks.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
90