PM7311 pmc-sierra, PM7311 Datasheet - Page 36

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
TRDY
TSX
Type
Tristate
Output
Input
Pin
No.
J1
K5
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
The transmit parity signal (TXPRTY) reflects the odd parity
calculated over the TXDATA[15:0] signals (regardless of
TMOD state). TXPRTY is only valid when TXDATA[15:0] are
valid.
Any-PHY Level 3 Mode:
The transmit parity signal (TXPRTY) reflects the odd parity
calculated over the TXDATA[7:0] signals. TXPRTY is only
valid when TXDATA[7:0] are valid.
Regardless of mode of operation TXPRTY is sampled on the
rising edge of TXCLK.
The transmit ready signal (TRDY) indicates the ability of the
transmit Any-PHY packet interface (APPI) to accept data.
When TRDY is set low, the transmit APPI is unable to accept
further data. When TRDY is set high, data provided on the
transmit APPI will be accepted by the FREEDM 84A1024L
device
If TRDY is driven low, the external controller must hold the
data on TXDATA until TRDY is driven high. TRDY may be
driven low for 0 or more TXCLK cycles before it is driven high.
TRDY is considered valid from two cycles after the start of
transfer until the cycle in which it is asserted high (it can only
backpressure once at the start of transfer).
A new transfer cannot be initiated earlier than one clock after
TRDY is sampled high.
TRDY is tristate during reset.
TRDY is updated on the rising edge of TXCLK.
Any-PHY Level 2 Mode
TRDY is valid one TXCLK cycle after TSX is sampled high.
TRDY is asserted by the FREEDM 84A1024L device, which
was selected by the in-band Any-PHY channel address on
TXDATA[15:0].
TRDY will only be driven high for one clock cycle, it is always
driven tristate one TXCLK cycle after it is driven high.
It is recommended that TRDY be connected externally to a
weak pull-up, e.g. 10 kW.
Any-PHY Level 3 Mode
TRDY is valid one TXCLK cycle after TSX is sampled high and
remains valid up to and including the cycle in which it is driven
high.
The transmit start of transfer signal (TSX) denotes the start of
data transfer on the transmit APPI.
The TSX signal is sampled on the rising edge of TXCLK.
Any-PHY Level 2 Mode
When the TSX signal is sampled high, the sampled word on
the TXDATA[15:0] signals contain the Any-PHY channel
address and priority associated with the data to follow. When
the TSX signal is sampled low, the sampled word on the
TXDATA[15:0] signals does not contain the Any-PHY channel
address/priority.
Any-PHY Level 3 Mode:
Released
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