PM7311 pmc-sierra, PM7311 Datasheet - Page 91

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Figure 34 Partial Packet Buffer Structure
The partial packet buffer processor is divided into three sections: reader, writer and roamer. The
roamer is a time-sliced state machine that tracks each HDLC channel’s FIFO buffer free space
and signals the writer to service a particular channel. The writer requests data from the EQM-12
block and transfers packet data from the EQM-12 to the associated HDLC channel FIFO. The
reader is a time-sliced state machine that transfers the HDLC information from an HDLC channel
FIFO to the HDLC processor in response to a request from the HDLC processor. If a buffer
under-run occurs for an HDLC channel, the reader informs the HDLC processor and purges the
rest of the packet. If a buffer overflow occurs for an HDLC channel (this can only happen if
EQM-12 disregards the requests), the THDL-12 overwrites the FIFO contents resulting in data
corruption on that particular HDLC channel. When an underflow or an overflow occurs, an
interrupt is generated and the cause of the interrupt may be read via the interrupt status register
using the microprocessor interface.
The writer and reader determine empty and full FIFO conditions using flags. Each block in the
partial packet buffer has an associated flag. The writer sets the flag after the block is written and
the reader clears the flag after the block is read. The flags are initialized (cleared) when the block
pointers are written using indirect block writes. The reader declares an HDLC channel FIFO
under-run whenever it tries to read data from a block without a set flag.
The FIFO algorithm of the partial packet buffer processor is based on per- HDLC channel
software programmable transfer size and free space trigger level. Instead of tracking the number
of full blocks in an HDLC channel FIFO, the processor tracks the number of empty blocks, called
Block 4095
Block 200
Block 0
Block 1
Block 2
Block 3
Partial Packet
Buffer RAM
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Block 4095
Block 200
Block 0
Block 1
Block 2
Block 3
Pointer RAM
Block
0xC8
0x03
0x01
XX
XX
XX
Released
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