PM7311 pmc-sierra, PM7311 Datasheet - Page 33

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
Table 3 Clock/Data Interface Signals (12 Pins)
Pin Name
RCLK[0]
RCLK[4]
RCLK[8]
RD[0]
RD[4]
RD[8]
TCLK[0]
TCLK[4]
TCLK[8]
TD[0]
TD[4]
TD[8]
Table 4 Any-PHY Packet Interface Signals (71 Pins)
Note: Any-PHY Level is s/w programmable.
Type
Type
Input
Input
Input
Output
Pin No.
AJ25
AH23
AJ21
AK25
AJ23
AK21
B13
C14
D15
A17
B18
A19
Pin
No.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
ADD bus signals, ADATA[7:0], ADP, APL and AV5.
All other Link Layer devices driving the SBI ADD bus should
monitor this signal (to detect multiple sources accidentally
driving the bus) and should cease driving the bus whenever a
conflict is detected.
AACTIVE is updated on the rising edge of REFCLK.
Function
The receive line clock signals (RCLK[8,4,0]) contain the
recovered line clock for the 3 independently timed links.
RCLK[n] must be externally gapped during the bits or time-
slots that are not part of the transmission format payload (i.e.
not part of the HDLC packet). RCLK[8,4,0] is nominally a
50% duty cycle clock between 0 and 52 MHz.
The RCLK[n] inputs are invalid and should be tied low when
their associated link is not configured for operation.
The receive data signals (RD[8,4,0]) contain the recovered
line data for the 3 independently timed links. RD[8,4,0]
contain HDLC packet data. For certain transmission formats,
RD[8,4,0] may contain placeholder bits or time-slots.
RCLK[n] must be externally gapped during the placeholder
positions in the RD[n] stream. The FREEDM 84A1024L
supports a maximum data rate of 52 Mbps on each link.
RD[8,4,0] is sampled on the rising edge of the corresponding
RCLK[8,4,0].
The transmit line clock signals (TCLK[8,4,0]) contain the
transmit clocks for the 3 independently timed links. TCLK[n]
must be externally gapped during the bits or time-slots that
are not part of the transmission format payload (i.e. not part
of the HDLC packet). TCLK[8,4,0] is nominally a 50% duty
cycle clock between 0 and 52 MHz.
The TCLK[n] inputs are invalid and should be tied low when
their associated link is not configured for operation
The transmit data signals (TD[8,4,0]) contain the transmit
data for the 3 independently timed links. TD[8,4,0] contains
HDLC packet data. For certain transmission formats,
TD[8,4,0] may contain placeholder bits or time-slots.
TCLK[n] must be externally gapped during the placeholder
positions in the TD[n] stream. The FREEDM 84A1024L
supports a maximum data rate of 52 Mbps on each link.
In normal operation, TD[8,4,0] is updated on the falling edge
of the corresponding TCLK[8,4,0] clock.
In loop back mode, TD[8,4,0] are updated on the falling edge
of the corresponding RCLK[8,4,0] clock.
Released
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