PM7311 pmc-sierra, PM7311 Datasheet - Page 276

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
14.12 Microprocessor Interface
Figure 58 Read Followed by Write Timing for Standard SSRAM Mode
The following diagrams illustrate the various handshaking required for microprocessor reads and
writes.
Figure 59 shows a single read and write operation to the non-burstable register space with bus
polarity set to 1. On the first cycle, BURSTB is sampled inactive; therefore, it is expected that
the cycle is a single data transfer, and the BLAST signal is of no significance. The subsequent 2
cycles have BURSTB sampled active hence the transfer cycle is terminated when both BLAST
and READYB are asserted. Note that between each transfer, there is a turn around cycle
provided by the external interface to ensure that there is no bus contention on back to back
transfers on the AD bus.
Figure 59 Read and Write to Non-burstable Register Space
Figure 60 shows a burst read and write operation (only valid for burstable registers) with bus
polarity set to 0. The first and third accesses illustrate transfers that are terminated by the
FREEDM 84A1024L via the assertion of BTERMB. The second and fourth accesses illustrate
transfers that are terminated by the external interface via the assertion of BLAST. Note that
BTERMB
BUSPOL
BURSTB
READYB
AD(31:0)
BLAST
ADSB
BCLK
CSB
WR
CC_RDDATA [35:0]
CC_WRDATA[35:0]
CC_ADDR[17:0]
1
CC_SELB
CC_WEB
SYSCLK
2
Read, 3 wait cycles
Read, 3 wait cycles
3
A
R0
1
4
R1
2
5
6
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Q0
3
7
D
Q1
4
8
9
Write, 1 wait cycle
Write, 1 wait cycle
A
5
10
W0
D0
6
11
D
12
W1
D1
7
13
R2
8
14
A
15
Read, 4 wait cycles
Read, 4 wait cycles
9
16
10
Q2
17
18
Released
19
D
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