PM7311 pmc-sierra, PM7311 Datasheet - Page 28

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
7
Description
The FREEDM 84A1024 device is a monolithic integrated circuit supporting highly channelized
termination of HDLC-framed Point to Point Protocol (PPP) and Frame Relay, including multi-
link variants.
On the Line side, the FREEDM 84A1024 device supports an SBI interface and three clock and
data interfaces for subrate DS3/E3 support. The FREEDM 84A1024L can support up to 1024
HDLC channels provisioned across these interfaces. On the system side, the FREEDM
84A1024L provides a Level 2 and Level 3 APPI presenting a channelized interface capable of
supporting full frame/packet transfers as well as fragment data transfers. Rate adaptation between
the line and system side interfaces is provided by external buffers.
The FREEDM 84A1024L terminates up to 1024 HDLC channels of HDLC framed PPP or Frame
Relay with speeds ranging from 56 Kbps to 52 Mbps in the ingress direction. HDLC channels
may contain a mix of protocols and speeds up to an aggregate of 156 Mbps. FREEDM 84A1024L
provides HDLC header removal, CRC checking and stripping. Data path termination including
frame/packet re-assembly and multi-link termination is provided in hardware.
In the egress direction, the FREEDM 84A1024L receives packets from the external controller.
The FREEDM 84A1024L provides support for ML-FR and ML-PPP protocols by fragmenting
transmitted packets, appending the appropriate sequence number and assigning the fragment to an
HDLC channel within the multi-link bundle. FREEDM 84A1024L is also capable of supporting
full packet transfer on up to 1024 HDLC channels that are not configured to support multi-link.
The HDLC processor within FREEDM 84A1024L encapsulates the data with HDLC flags, CRC
bytes and performs the appropriate bit stuffing.
The FREEDM 84A1024L supports two levels of priority for egress traffic on HDLC channels that
are not configured as part of a multi-link bundle. The priority of each packet received from the
external controller is indicated by an additional address bit in the Any-PHY in-band address
header word. Packets received with different priorities on a given channel are stored in separate
queues for transmission. If the FREEDM 84A1024L is configured to fragment low-priority
packets, any high priority data received following a low priority packet will be transmitted at the
first available opportunity, and will be interleaved between fragments of the low priority packet if
possible.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
28