PM7311 pmc-sierra, PM7311 Datasheet - Page 37

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
TEOP
TMOD
TERR
RXCLK
RXADDR[0]
RXADDR[1]
RXADDR[2]
RXADDR[3]
Type
Input
Input
Input
Input
Input
Pin
No.
J2
J3
J4
AE5
AF2
AE4
AE3
AE2
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
When the TSX signal is sampled high, the sampled byte on
the TXDATA[7:0] signals contain the most significant byte of
the Any-PHY channel address and priority associated with the
data to follow. When the TSX signal is sampled low, the
sampled word on the TXDATA[7:0] signals does not contain
the first byte of the Any-PHY channel address/priority.
The transmit end of packet signal (TEOP) denotes the end of
a packet. TEOP is only valid during data transfer.
TEOP is sampled on the rising edge of TXCLK.
Any-PHY Level 2 Mode
When TEOP is sampled high, the data on TXDATA[15:0] is
the last word of a packet. When TEOP is sampled low, the
data on TXDATA[15:0] is not the last word of a packet
(fragment).
Any-PHY Level 3 Mode:
When TEOP is sampled high, the data on TXDATA[7:0] is the
last byte of a packet (fragment). When TEOP is sampled low,
the data on TXDATA[7:0] is not the last byte of a packet
(fragment).
Any-PHY Level 2 Mode
The transmit word modulo signal (TMOD) indicates the size of
the current word on TXDATA[15:0]. TMOD is only valid when
TEOP is sampled high. When TMOD is sampled high and
TEOP is sampled high, only the TXDATA[15:8] signals contain
valid data and the TXDATA[7:0] signals are invalid. When
TMOD is sampled low and TEOP is sampled high, the
complete word on TXDATA[15:0] contains valid data. TMOD
must be set low when TEOP is set low.
TMOD is sampled on the rising edge of TXCLK.
Any-PHY Level 3 Mode:
TMOD is not used. The last valid byte of data on TXDATA[7:0]
is sampled when TEOP is sampled high.
The transmit error signal (TERR) indicates that the current
packet is erred and should be aborted. TERR is only valid
when TEOP is sampled high. When TERR is sampled high
and TEOP is sampled high, the current packet is erred and the
FREEDM 84A1024L will respond accordingly. When TERR is
sampled low and TEOP is sampled high, the current packet is
not erred. TERR must be set low when TEOP is set low.
TERR is sampled on the rising edge of TXCLK.
The receive clock signal (RXCLK) provides timing for the
receive Any-PHY packet interface (APPI).
Any-PHY Level 2 Mode
RXCLK is a nominally 50% duty cycle, 25 to 52 MHz clock.
Any-PHY Level 3 Mode:
RXCLK is a nominally 50% duty cycle, 50 to 104 MHz clock.
Any-PHY Level 2 Mode:
The receive address signals (RXADDR[3:0]) serve two
functions – device polling and device selection. When polling,
the RXADDR[3:0] signals provide an address for polling a
Released
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