PM7311 pmc-sierra, PM7311 Datasheet - Page 147

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
INVERT
INHIBIT
7BIT
The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert
the outgoing HDLC stream. The value of INVERT to be written to the channel provision
RAM, in an indirect channel write operation, must be set up in this register before triggering
the write. When INVERT is set to one, the outgoing HDLC stream is logically inverted. The
outgoing HDLC stream is not inverted when INVERT is set to zero. INVERT reflects the
value written until the completion of a subsequent indirect channel read operation.
The channel FIFO expedite inhibit bit (INHIBIT) informs the partial packet processor that the
channel has less priority than other channels when requesting data from the EQM-12. The
value of INHIBIT to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. Channel FIFOs with
INHIBIT set to one cannot make expedited requests for data to the EQM-12. When INHIBIT
is set to zero, both normal and expedited requests can be made to the EQM-12. Channels with
HDLC data rates significantly slower than other channels should have INHIBIT set to one.
INHIBIT reflects the value written until the completion of a subsequent indirect channel read
operation.
The least significant stuff enable bit (7BIT) configures the HDLC processor to stuff the least
significant bit of each octet in the outgoing channel stream. The value of 7BIT to be written
to the channel provision RAM, in an indirect channel write operation, must be set up in this
register before triggering the write. When 7BIT is set high, the least significant bit (last bit of
each octet transmitted) does not contain channel data and is forced to the value configured by
the BIT8 register bit. When 7BIT is set low, the entire octet contains valid data and BIT8 is
ignored. 7BIT reflects the value written until the completion of a subsequent indirect channel
read operation.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
147