PM7311 pmc-sierra, PM7311 Datasheet - Page 12

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Figure 29 DRAM Configuration for the Chunk Buffer Interface ..................................................85
Figure 30 DRAM Configuration for the Re-Sequencing Memory Interface ................................86
Figure 31 4-Bank Configuration for 8 MB of ZBT or Standard SSRAM......................................87
Figure 32 2-Bank Configuration for Eight Mbit/s of ZBT-Compatible or Standard
Figure 33 1-Bank Configuration for Eight Mbit/s of ZBT or Standard SSRAM ...........................89
Figure 34 Partial Packet Buffer Structure ...................................................................................91
Figure 35 Boundary Scan Architecture .....................................................................................259
Figure 36 TAP Controller Finite State Machine ........................................................................260
Figure 37 T1/E1 Drop Bus Functional Timing...........................................................................263
Figure 38 DS3 Drop Bus Functional Timing .............................................................................263
Figure 39 DS3 Add Bus Adjustment Request Functional Timing .............................................264
Figure 40 Receive Link Timing .................................................................................................264
Figure 41 Transmit Link Timing ................................................................................................265
Figure 42 Receive APPI Timing (Normal Transfer 16 bit 52 MHz) ...........................................265
Figure 43 Receive APPI Timing (Auto Deselection) .................................................................267
Figure 44 Receive APPI Timing (Optimal Reselection) ............................................................267
Figure 45 Receive APPI Timing (Boundary Condition).............................................................268
Figure 46 Transmit APPI Timing (Normal Transfer) .................................................................269
Figure 47 Transmit APPI Timing (Special Conditions) .............................................................270
Figure 48 Transmit APPI Poll Timing........................................................................................270
Figure 49 Receive APPI Timing (Normal Transfer 8 bit 104 MHz) ...........................................271
Figure 50 Transmit APPI Timing Any-PHY Level 3 (Normal Transfer).....................................272
Figure 51 Transmit APPI Timing Any-PHY Level 3 (Special Condition)...................................273
Figure 52 Transmit APPI Polling Timing (Any-PHY Level 3) ....................................................273
Figure 53 Read Timing for Re-Sequencing Memory ................................................................274
Figure 54 Write Timing Re-Sequencing Memory......................................................................274
Figure 55 Read Timing for Chunk Buffer Memory ....................................................................275
Figure 56 Write Timing for Chunk Buffer Memory ....................................................................275
Figure 57 Read Followed by Write Timing for ZBT Mode.........................................................275
Figure 58 Read Followed by Write Timing for Standard SSRAM Mode ...................................276
Figure 59 Read and Write to Non-burstable Register Space ...................................................276
Figure 60 Read and Write to Burstable Address Space ...........................................................277
Figure 61 Consecutive Write Accesses Using WRDONEB ......................................................277
Figure 62 SBI336 Drop Bus Input Interface Timing ..................................................................283
Figure 63 SBI336 Add Bus Input Interface Timing ...................................................................284
Figure 64 SBI336 Add Bus Output Interface Timing.................................................................285
SSRAM ..................................................................................................................................88
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
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