PM7311 pmc-sierra, PM7311 Datasheet - Page 150

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
IDLE
TRANS
The inter-frame time fill bit (IDLE) configures the HDLC processor to use flag bytes or
HDLC idle as the inter-frame time fill between HDLC packets. The value of IDLE to be
written to the channel provision RAM, in an indirect channel write operation, must be set up
in this register before triggering the write. When IDLE is set low, the HDLC processor uses
flag bytes as the inter-frame time fill. When IDLE is set high, the HDLC processor uses
HDLC idle (all one’s bit with no bit-stuffing pattern is transmitted) as the inter-frame time
fill. IDLE reflects the value written until the completion of a subsequent indirect channel
read operation.
The indirect transmission start bit (TRANS), in concert with the LEVEL[3:0] bits, configure
the various channel FIFO free space levels which trigger the HDLC processor to start
transmission of a HDLC packet as well as trigger the partial packet buffer to request data
from the upstream device as shown in the following table. The transmission start mode to be
written to the channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. TRANS reflects the value written until the completion of
a subsequent indirect channel read operation.
The HDLC processor starts transmitting a packet when the channel FIFO free space is less
than or equal to the level specified in the appropriate Start Transmission Level column of the
following table or when an end of a packet is stored in the channel FIFO. When the channel
FIFO free space is greater than or equal to the level specified in the Starving Trigger Level
column of the following table and the HDLC processor is transmitting a packet and an end of
a packet is not stored in the channel FIFO, the partial packet buffer makes expedited requests
to the upstream device to retrieve XFER[3:0] + 1 blocks of data.
To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or
equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the
channel transfer size can be set, such that, the total number of blocks in the logical channel
FIFO minus the start transmission level is an integer multiple of the channel transfer size.
The starving trigger level must always be set to a number of blocks greater than or equal to
the channel transfer size.
Table 21 Level[3:0]/TRANS Settings
LEVEL[3:0]
0010
0011
0100
0101
Starving
Trigger Level
4 Blocks
(64 bytes free)
6 Blocks
(96 bytes free)
8 Blocks
(128 bytes free)
12 Blocks
(192 bytes free)
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Start Transmission
Level (TRANS=0)
Invalid
4 Blocks
(64 bytes free)
6 Blocks
(96 bytes free)
8 Blocks
(128 bytes free)
Start Transmission
Level (TRANS=1)
2 Blocks
(32 bytes free)
Invalid
4 Blocks
(64 bytes free)
6 Blocks
(96 bytes free)
Released
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