PM7311 pmc-sierra, PM7311 Datasheet - Page 148

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x38C: THDL Indirect Channel Data #3
This register contains data read from the channel provision RAM after an indirect read operation
or data to be inserted into the channel provision RAM in an indirect write operation.
XFER[3:0]
The indirect channel transfer size (XFER[3:0]) specifies the minimum FIFO free space, less
1, before the partial packet processor begins requesting data from the DMA port. The channel
transfer size to be written to the channel provision RAM, in an indirect write operation, must
be set up in this register before triggering the write. When the channel FIFO free space
reaches the limit specified by XFER[3:0], the partial packet processor will make a request to
the DMA port for one XFER[3:0] amount of data. FIFO free space is measured in the number
of blocks with each block being 16 bytes in size. XFER[3:0] reflects the value written until
the completion of a subsequent indirect channel read operation.
XFER[3:0] must be less than or equal to the start transmission level specified by LEVEL[3:0]
and TRANS.
Bit
Bit 31
To
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
TRANS
IDLE
Unused
Unused
LEVEL[3]
LEVEL[2]
LEVEL[1]
LEVEL[0]
FLAG[2]
FLAG[1]
FLAG[0]
Unused
XFER[3]
XFER[2]
XFER[1]
XFER[0]
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
148