PM7311 pmc-sierra, PM7311 Datasheet - Page 257

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
12
12.1 Test Mode Registers
12.2 JTAG Test Port
Test Features Description
The FREEDM 84A1024L also supports a standard IEEE 1149.1 five signal JTAG boundary scan
test port for use in board testing. All device inputs may be read and all device outputs may be
forced via the JTAG test port.
Test mode registers are used to apply test vectors to the DLL during production testing of the
FREEDM 84A1024L. Production testing is enabled by asserting the PMCTEST pin. During
production tests, FREEDM 84A1024L registers are selected by the TA[12:0] pins. Read accesses
are enabled by asserting TRDB low while write accesses are enabled by asserting TWRB low.
Test mode register data is conveyed on the TDAT[15:0] pins. Test mode registers (as opposed to
normal mode registers) are selected when TA[12]/TRS is set high.
Table 50 Test Mode Register Memory Map
Address TA[12:0]
0x0000 - 0x0EFF
0x0F00 - 0x0F1F
0x1F20 - 0x1F2C
0x1F2D - 0x1FFF
Notes on Test Mode Register Bits:
1.
2.
The FREEDM 84A1024L JTAG Test Access Port (TAP) allows access to the TAP controller and
the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP,
device input logic levels can be read, device outputs can be forced, the device can be identified
and the device scan path can be bypassed. For more details on the JTAG port, please refer to the
Operations section.
Writing values into unused register bits has no effect. However, to ensure software compatibility with
future, feature-enhanced versions of the product, unused register bits must be written with logic zero.
Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits
should be masked off by software when read.
Writeable test mode register bits are not initialized upon reset unless otherwise noted.
Register
Normal Mode Registers
Reserved
DLL Test Registers
Reserved
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
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