PM7311 pmc-sierra, PM7311 Datasheet - Page 92

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.9.14
free space, as well as the number of end of packets stored in the FIFO. Recording the number of
empty blocks instead of the number of full blocks reduces the amount of information the roamer
must store in its state RAM.
The partial packet roamer records the FIFO free space and end-of-packet count for all HDLC
channel FIFOs. When the reader signals that a block has been read, the roamer increments the
FIFO free space and sets a per- HDLC channel request flag if the free space is greater than the
hungry or starving threshold. The roamer pushes this status information to the EQM to indicate
that it can accept at least one transfer of data. The roamer also decrements the end-of-packet
count when the reader signals that it has passed an end of a packet to the HDLC processor. The
roamer listens to control information from the EQM-12 to decide which HDLC channel FIFO
requests data from the EQM block. The roamer informs the partial packet writer of the HDLC
channel FIFO to process and the FIFO free space. The writer sends a request for data to the
EQM-12 block, writes the response data to the HDLC channel FIFO, and sets the block full flags.
The writer reports back to the roamer the number of blocks and end-of-packets transferred. The
maximum amount of data transferred during one request is set by XFER.
The roamer round-robins between all HDLC channels FIFOs and pushes the status to the EQM-
12 block. The status consists of two pieces of information: (1) is there space in the HDLC
channel FIFO for at least 32 bytes of data, and (2) is this channel FIFO at risk of underflowing.
The configuration of the HDLC processor is accessed using indirect channel read and write
operations as well as indirect block read and write operations. When an indirect operation is
performed, the information is accessed from RAM during a null clock cycle identified by the
TCAS-12 block. Writing new provisioning data to an HDLC channel resets the entire state
vector.
Transmit Channel Assignor (TCAS-12)
The Transmit Channel Assignor block (TCAS-12) processes up to 1024 HDLC channels. Data for
all HDLC channels is sourced from a single byte-serial stream from the Transmit HDLC
Controller / Partial Packet Buffer block (THDL-12). The TCAS-12 demultiplexes the data and
assigns each byte to any one of 84 links. When sending data to the SBI block, each link may be
configured to support channelized T1/J1/E1 traffic, unchannelized DS3 traffic or unframed traffic
at T1/J1, E1, DS3 or Fractional DS3 rates. When sending data to the TD outputs, links 0, 4 and 8
support unchannelized data at arbitrary rates up to 52 Mbps. Each link is independent and has its
own associated clock.
The 84 TCAS links have a fixed relationship to the SPE and tributary numbers on the SBI ADD
BUS as shown in the following table.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
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