PM7311 pmc-sierra, PM7311 Datasheet - Page 50

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
BUSPOL
Table 9 Miscellaneous Interface Signals (10 Pins)
Pin Name
SYSCLK
RSTB
PMCTEST
DLLTEST
SCAN_EN
TCK
TMS
TDI
TDO
Type
Input
Input
Input
Input
Input
Input
Input
Input
Tristate
Output
Type
Input
Pin No.
H1
H3
H4
H2
D13
G3
G4
H5
G1
Pin No.
E13
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
The system clock (SYSCLK) provides timing for the core
logic. SYSCLK is nominally a 50% duty cycle clock of
frequency 100 MHz ±50ppm.
The active low reset signal (RSTB) signal provides an
asynchronous FREEDM 84A1024L reset. RSTB is an
asynchronous input. When RSTB is set low, all FREEDM
84A1024L registers are forced to their default states. This
signal must be held low for a minimum of 320ns. In
addition, all SBI, APPI and µP interface output pins are
forced tristate and will remain tristated until RSTB is set
high.
RSTB must be asserted until the SDRAMs are out of
reset.
The PMC production test enable signal (PMCTEST)
places the FREEDM 84A1024L in scan mode. PMCTEST
must be tied low for normal operation (and during BIST).
The DLL test enable signal (DLLTEST) places the DLL in
scan mode. DLLTEST must be tied low for normal
operation (and during BIST).
The PMC Production SCAN_EN signal is used during
scan mode. It must be tied low for normal operation.
The test clock signal (TCK) provides timing for test
operations that can be carried out using the IEEE
P1149.1 test access port. TMS and TDI are sampled on
the rising edge of TCK. TDO is updated on the falling
edge of TCK.
The test mode select signal (TMS) controls the test
operations that can be carried out using the IEEE
P1149.1 test access port. TMS is sampled on the rising
edge of TCK. TMS has an integral pull up resistor.
The test data input signal (TDI) carries test data into the
FREEDM 84A1024L via the IEEE P1149.1 test access
port. TDI is sampled on the rising edge of TCK.
TDI has an integral pull up resistor.
The test data output signal (TDO) carries test data out of
the FREEDM 84A1024L via the IEEE P1149.1 test
access port. TDO is updated on the falling edge of TCK.
TDO is a tristate output, which is inactive except when
scanning of data is in progress.
the WR and BLAST inputs to FREEDM 84A1024L.
When high, the BLAST pin is active high (high indicates
the last word of the burst) and the WR pin is active low
(low indicates write).
When low, the BLAST pin is active low (low indicates the
last word of the burst) and the WR pin is active high (high
indicates write).
BUSPOL is sampled on the rising edge of BCLK.
Function
Bus Control Polarity. This signal indicates the polarity of
Released
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