PM7311 pmc-sierra, PM7311 Datasheet - Page 62

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.2 Memory Port
10.2.1
10.2.2
Writing
Write operations to external memory can be performed in up to 4-long word bursts to the memory
port. The procedure is as follows:
1. The microprocessor polls the MPBusy bit of the Memory Port Control register (or monitors
2. The microprocessor writes up to 4 long words of data into the write burst register array and
3. The microprocessor writes a command to the memory burst control register. The command
4. FREEDM 84A1024L arbitrates for the appropriate memory, performs the write to memory,
Reading
Reads from external memory can be performed in 4-long word bursts from the memory port. The
procedure is as follows:
1. The microprocessor issues a read command to the Memory Port Control register. The
2. FREEDM 84A1024L arbitrates for the appropriate memory, performs the read from memory
3. The microprocessor polls the MPBusy bit of the Memory Port Control register status (or
4. The microprocessor reads up to 4 long words of data from the read burst register array and
the MPISTATI interrupt) to verify that the previous write is complete. Alternatively, this step
may be skipped if the system application allows FREEDM 84A1024L to withhold the
READYB for write accesses. In this case, FREEDM 84A1024L will delay write operations
to the write burst registers and overflow register until the previous write command is
complete.
the overflow register (for 48-bit accesses).
indicates the aperture, the quad-long word address in memory, the type of write (masked or
unmasked), and the 4 long word enables. MPBusy will be set until the write is complete.
and clears the MPBusy bit in the control register.
command indicates aperture, the quad-long word address in memory, and 4 long word
enables. The MPBusy bit will be set by the FREEDM 84A1024L.
and loads the read burst registers with the results, and clears the MPBusy bit in the control
register.
monitors the MPISTATI interrupt) to verify that the read is complete. Alternatively, this step
may be skipped if the system application can tolerate long response times for read accesses.
In this case, FREEDM 84A1024L will delay read operations from the read burst registers and
overflow register until the read command is complete.
the overflow register (for 48-bit accesses).
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
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