PM7311 pmc-sierra, PM7311 Datasheet - Page 81

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.9.8
FIFO Storage and Control
The FIFO block temporarily stores Any-PHY channel data during transfer across the Rx APPI. A
separate storage element samples the 16-bit address prepend to associate the data in that FIFO
with a specific Any-PHY channel. This Any-PHY channel ID is prepended in-band as the first
word of every burst data transfer across the Rx APPI. In Any-PHY Level-3 mode, the address
prepend is appended on the first two bytes of the packet.
The writer controller provides a means for writing data into the FIFO. The reader controller
provides a means of reading data out of the FIFO onto the Rx APPI. When selected to do so the
reader controller will read the data out of the FIFO. To prevent from overloading the Rx APPI
with several small bursts of data, the RAPI-12 automatically deselects after every burst transfer.
This provides time for the upper layer device to detect an end of packet indication and possibly
reselect a different FREEDM 84A1024L device without having to store the extra word or two that
may have been output onto the Rx APPI during the time it took for deselection.
The RAPI-12 provides packet status information on the Rx APPI at the end of every packet
transfer. The RAPI-12 asserts RERR at the end of packet reception (REOP high) to indicate that
the packet is in error. The RAPI-12 may optionally be programmed to overwrite RXDATA[7:0]
of the final word of each packet transfer (REOP is high) with the status of packet reception when
that packet is erred (RERR is high). Overwriting of status information is enabled by setting the
STATEN bit in the RAPI-12 control register.
Polling Control and Management
The RAPI-12 only responds to Any-PHY channel polls that match the device base address bits
programmed in the RAPI-12 Base Address register. A positive poll response indicates that the
FIFO is ready to be selected to transfer this data across the Rx APPI.
Transmit Any-PHY Interface (TAPI-12)
The Transmit Any-PHY Interface (TAPI-12) provides a low latency path for transferring data
from the Transmit Any-PHY Packet Interface (Tx APPI) to the TFRAG engine or the EQM. The
TAPI-12 contains a FIFO block for latency control as well as to segregate the APPI timing
domain from the SYSCLK timing domain. The TAPI-12 contains the necessary logic to manage
and respond to Any-PHY channel polling from an upper layer device.
The TAPI-12 supports ANY-PHY Level-2, and ANY-PHY Level-3 modes of operation. When
operating at 104 MHz the lower 8 bits of the data are active.
FIFO Storage and Control
The FIFO block temporarily stores Any-PHY channel data during transfer across the Tx APPI.
TAPI-12 burst data transfers are transaction based on the writer side of the FIFO.
The first word of each burst transfer contains the address/priority prepend field. A separate
storage element samples the address prepend to associate the data with a specific Any-PHY
channel. The address prepend is compared to the base and range registers. The address prepend
must correspond to an Any-PHY channel that is supported by the FREEDM 84A1024L for the
TAPI-12 to respond to the data transaction on the Tx APPI.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
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