PM7311 pmc-sierra, PM7311 Datasheet - Page 46

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Pin Name
CCSELB
CCBSELB
Table 7 Chunk Buffer SDRAM Interface (67 Signals)
Pin Name
CBCSB
CBRASB
CBCASB
CBWEB
CBADD[0]
CBADD[1]
CBADD[2]
CBADD[3]
CBADD[4]
CBADD[5]
CBADD[6]
CBADD[7]
CBADD[8]
CBADD[9]
CBADD[10]
CBADD[11]
CBADD[12]
CBBS[0]
CBBS[1]
Type
Output
Output
Output
Output
Output
Output
Type
Output
Output
Pin
No.
E29
K29
Pin No.
AF5
AG2
AF4
AG3
AH7
AK6
AG7
AJ6
AL5
AH6
AK5
AG6
AJ5
AK4
AH5
AG4
AH2
AG1
AF3
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
asserted high, the cycle type is a read. When CCWEB is
asserted low, the cycle type is a write.
CCWEB is updated on the rising edge of SYSCLK.
Context Memory SSRAM Chip Enable Bar. CCSELB initiates
an access. When CCSELB is asserted low, the external
SSRAM samples the address and CCWEB asserted by the
FREEDM 84A1024L.
CCSELB is updated on the rising edge of SYSCLK.
SSRAM Bank Select
This active low output is provided to enable glueless
connection to 4 banks of Standard/ZBT SSRAM:
CCBSELB is the inverse of CCADD[16]. CCBSELB and
CCADD[16:17] are used to select 4 banks when 64x36
devices are used.
Function
Chunk Buffer SDRAM Chip Select Bar. CBCSB, CBRASB,
CBCASB, and CBWEB define the command being sent to
the SDRAM.
CBCSB is updated on the rising edge of SYSCLK.
Chunk Buffer SDRAM Row Address Strobe Bar. CBCSB,
CBRASB, CBCASB, and CBWEB define the command
being sent to the SDRAM.
CBRASB is updated on the rising edge of SYSCLK.
Chunk Buffer SDRAM Column Address Strobe Bar.
CBCSB, CBRASB, CBCASB, and CBWEB define the
command being sent to the SDRAM.
CBCASB is updated on the rising edge of SYSCLK.
Chunk Buffer SDRAM Write Enable Bar. CBCSB,
CBRASB, CBCASB, and CBWEB define the command
being sent to the SDRAM.
CBWEB is updated on the rising edge of SYSCLK.
Chunk Buffer SDRAM Address. The Chunk Buffer SDRAM
address outputs identify the row address (CBADD12:0])
and column address (CBADD[8:0]) for the locations
accessed.
CBADD[12:0] is updated on the rising edge of SYSCLK.
Chunk Buffer SDRAM Bank Select. The bank select signal
determines which bank of a dual/quad bank Chunk Buffer
SDRAM chip is active. CBBS[1:0] is generated along with
the row address when CBRASB is asserted low.
Released
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