p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 24

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 5.8 Interrupt Control for DTC ........................................................................................... 98
Figure 5.9 Block Diagram of Address Break Function .............................................................. 100
Figure 5.10 Examples of Address Break Timing........................................................................ 102
Figure 5.11 Conflict between Interrupt Generation and Disabling............................................. 103
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 106
Figure 6.2 IOS Signal Output Timing ........................................................................................ 112
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 113
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 114
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 116
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 117
Figure 6.7 Example of Wait State Insertion Timing (Pin Wait Mode) ....................................... 119
Figure 6.8 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)...................... 120
Figure 6.9 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)...................... 121
Figure 6.10 Examples of Idle Cycle Operation .......................................................................... 122
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC ............................................................................................. 126
Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 133
Figure 7.3 DTC Register Information Location in Address Space............................................. 134
Figure 7.4 DTC Operation Flowchart......................................................................................... 136
Figure 7.5 Memory Mapping in Normal Mode .......................................................................... 137
Figure 7.6 Memory Mapping in Repeat Mode ........................................................................... 138
Figure 7.7 Memory Mapping in Block Transfer Mode .............................................................. 139
Figure 7.8 Chain Transfer Operation.......................................................................................... 140
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 141
Figure 7.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ...................................... 142
Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 142
Section 8 I/O Ports
Figure 8.1 Noise Cancel Circuit ................................................................................................. 177
Figure 8.2 Conceptual Diagram of Noise Cancel Operation ...................................................... 177
Section 9 8-Bit PWM Timer (PWM)
Figure 9.1 Block Diagram of PWM Timer................................................................................. 184
Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000).......... 193
Figure 9.3 Example of PWM Setting.......................................................................................... 194
Figure 9.4 Example when PWM is Used as D/A Converter....................................................... 194
Rev. 1.00 Sep. 21, 2006 Page xxiv of xxxviii