p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 533

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

(f)
The current frequency of the CPU clock is set to the FPEFEQ parameter (general register ER0).
The settable range of the FPEFEQ parameter is 8 to 20 MHz. When the frequency is set out of this
range, an error is returned to the FPFR parameter of the initialization program and initialization is
not performed. For details on the frequency setting, see the description in section 19.3.2 (2) (a),
Flash programming/erasing frequency control parameter (FPEFEQ: general register ER0 of CPU).
(g)
When a programming program is downloaded, the initialization program is also downloaded to the
on-chip RAM. There is an entry point for the initialization program in the area from the start
address of a download destination specified by FTDAR + 32 bytes. The subroutine is called and
initialization is executed by using the following steps.
• The general registers other than R0L are saved in the initialization program.
• R0L is a return value of the FPFR parameter.
• Since the stack area is used in the initialization program, a 128-byte stack area at the maximum
• Interrupts can be accepted during the execution of the initialization program. Note however
(h) The return value in the initialization program, FPFR (general register R0L) is
(i)
The stipulated voltage is applied for the stipulated time when programming or erasing. If
interrupts occur or a bus master other than the CPU gets the bus during this period, a voltage pulse
exceeding the specification may be applied, thus damaging flash memory. Accordingly, interrupts
must be disabled and a bus master other than the CPU, such as the DTC, must not be allowed.
To disable interrupts, bit 7 (I) in the condition code register (CCR) of the CPU should be set to B'1
in interrupt control mode 0, or bits 7 and 6 (I and UI) in the condition code register (CCR) of the
CPU should be set to B'11 in interrupt control mode 1. This enables interrupts other than NMI to
be held and not executed.
MOV.L
JSR
NOP
must be allocated in RAM.
that the program storage area and stack area in the on-chip RAM, and register values must not
be rewritten.
Set the operating frequency to the FPEFEQ parameter for initialization.
Initialization
determined.
All interrupts and the use of a bus master other than the CPU are prohibited.
#DLTOP+32,ER2
@ER2
; Set entry address to ER2
; Call initialization routine
Section 19 Flash Memory (0.18-µm F-ZTAT Version)
Rev. 1.00 Sep. 21, 2006 Page 495 of 658
REJ09B0310-0100