p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 554
p2125vps20
Manufacturer Part Number
p2125vps20
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.P2125VPS20.pdf
(700 pages)
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Section 19 Flash Memory (0.18-µm F-ZTAT Version)
4. When a bus master other than the CPU, such as the DTC, acquires the bus during
Error protection is cancelled only by a reset or a transition to hardware-standby mode.
Note that the reset should be released after a reset period of 100 µs which is longer than normal.
Since high voltages are applied during programming/erasing of the flash memory, some voltage
may remain after the error-protection state has been entered. For this reason, it is necessary to
reduce the risk of damage to the flash memory by extending the reset period so that the charge is
released.
The state transition diagram in figure 19.16 shows transitions to and from the error-protection
state.
Rev. 1.00 Sep. 21, 2006 Page 516 of 658
REJ09B0310-0100
Error occurred
programming/erasing
Programming/erasing enabled
Programming/erasing disabled
Program mode
Error-protection state
Erase mode
Read disabled
FLER = 0
Read enabled
FLER = 1
Figure 19.16 Transitions to Error-Protection State
Software-standby mode
canceled
Software standby mode
RES = 0 or STBY = 0
Programming/erasing disabled
Error-protection state
RES = 0 or
STBY = 0
(Software standby)
Programming/erasing interface
registers are in the initial state.
Programming/erasing disabled
Read disabled
(Hardware protection)
FLER = 1
Reset or hardware
standby mode
Read disabled
FLER = 0
Programming/erasing interface
registers are in the initial state.
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