p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 374

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface (SCI)
15.4.5
Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
Figure 15.7 shows a sample flowchart for transmission in asynchronous mode.
Rev. 1.00 Sep. 21, 2006 Page 336 of 658
REJ09B0310-0100
written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt
request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to
TDR before transmission of the current transmit data has finished, continuous transmission can
be enabled.
multiprocessor bit (may be omitted depending on the format), and stop bit.
serial transmission of the next frame is started.
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
TXI interrupt
request generated
TDRE
TEND
Data Transmission (Asynchronous Mode)
Figure 15.6 Example of SCI Transmit Operation in Asynchronous Mode
1
Start
bit
0
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt handling routine
D0
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
1 frame
Data
D7
Parity
bit
0/1
TXI interrupt
request generated
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
TEI interrupt
request generated
0/1
Stop
bit
1
Idle state
(mark state)
1