p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 384

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface (SCI)
Rev. 1.00 Sep. 21, 2006 Page 346 of 658
REJ09B0310-0100
No
No
No
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)
Read ORER and FER flags in SSR
Read ORER and FER flags in SSR
Read receive data in RDR
Read receive data in RDR
Set MPIE bit in SCR to 1
Clear RE bit in SCR to 0
Read RDRF flag in SSR
Read RDRF flag in SSR
All data received?
FER ∨ ORER = 1
FER ∨ ORER = 1
This station’s ID?
End of reception
Start reception
Initialization
RDRF = 1
RDRF = 1
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
Error processing
[3]
[1]
[2]
(Continued on
next page)
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[Legend]
∨ : Logical OR
Note: The SMR, SCR, SCMR, and BRR
SCI initialization:
The RxD pin is automatically designated as
the receive data input pin.
ID reception cycle:
Set the MPIE bit in SCR to 1.
SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again, and clear the RDRF flag to 0.
If the data is this station’s ID, clear the RDRF
flag to 0.
SCI status check and data reception:
Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
Receive error processing and break detection:
If a receive error occurs, read the ORER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the ORER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RxD pin value.
registers should not be written to
during the period from the start to the
end of reception. This does not apply
to the processing at step [6].