p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 483

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

17.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D
conversion. The ADST bit can be set at the same time the operating mode or analog input channel
is changed.
17.4.1
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by
2. When A/D conversion is completed, the result is transferred to the A/D data register
3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to
4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit
17.4.2
In scan mode, A/D conversion is to be performed sequentially on the specified channels (max.
four channels). Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not automatically cleared to 0 so steps [2] and [3] are repeated as long as the
software or an external trigger input.
corresponding to the channel.
1 at this time, an ADI interrupt request is generated.
is automatically cleared to 0, and the A/D converter enters wait state.
conversion starts on the first channel in the group (AN0 when the CH2 bit in ADCSR is 0, or
AN4 when the CH2 bit in ADCSR is 1).
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion from the first channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
Operation
Single Mode
Scan Mode
Rev. 1.00 Sep. 21, 2006 Page 445 of 658
Section 17 A/D Converter
REJ09B0310-0100