p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 475

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

16.6.1
While the WAIT bit in ICMR is set to 1 and WAIT in master mode, if the interrupt flag of the
IRIC bit is cleared from 1 to 0 between the falling edge of the 7th clock and the falling edge of the
8th clock, the clock pulse of the 9th clock may be output continuously due to the failure to insert a
wait after the falling edge of the 8th clock.
When the wait function is used in master mode, clear the IRIC flag after the IRIC flag is set to 1
on the falling edge of the 9th clock and before the rising edge of the 7th clock (the counter value
of BC2 to BC0 should be 2 or greater).
If the clearing of the IRIC flag is delayed due to the interrupt or other processes and the value of
the RC counter is changed to 1 or 0, confirm that the SCL pins are in the L state after the counter
values of BC2 to BC0 are cleared to 0, and then clear the IRIC flag (see figure 16.36).
Note: This limitation on use can be cleared by setting the FNC1 and FNC0 bits in ICXR to B'11.
16.6.2
The IIC operation can be enabled or disabled using the module stop control register. The initial
setting is for the IIC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 22, Power-Down Modes.
SDA
SCL
BC2 to BC0
IRIC
(operation example)
Note on Wait Function in Master Mode
Module Stop Mode Setting
A
9
0
Figure 16.36 IRIC Flag Clear Timing in Wait Operation
1
7
IRIC flag clearing possible
2
6
Transmit/receive data
3
5
4
4
5
3
IRIC flag clear impossible
6
2
7
1
8
Confirm SCL = L
IRIC flag clearing possible
Rev. 1.00 Sep. 21, 2006 Page 437 of 658
Clear IRIC
0
A
Section 16 I
9
1
receive data
7
Transmit/
2
6
2
C Bus Interface (IIC)
When BC2 to BC0 ≥ 2,
clear IRIC
REJ09B0310-0100
3
5