p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 470

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
9. Note on when I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
10. Note on IRIC flag clear when the wait function is used
Rev. 1.00 Sep. 21, 2006 Page 432 of 658
REJ09B0310-0100
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
ICXR.
2
SCL
SDA
IRIC
C Bus Interface (IIC)
2
C bus interface stop condition instruction is issued
9th clock
V
IH
Figure 16.31 Stop Condition Issuance Timing
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination
Secures a high period
[2] Stop condition instruction issuance
Stop condition generation
2
C bust interface