p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 461

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

16.4.9
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.28 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
16.4.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch
Register (DDCSWR).
(1)
The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Scope of Initialization
Noise Canceller
SCL or
SDA input
signal
Sampling
clock
Figure 16.28 Block Diagram of Noise Canceler
D
Sampling clock
System clock
cycle
Latch
C
Q
D
Latch
C
Q
Rev. 1.00 Sep. 21, 2006 Page 423 of 658
detector
Match
Section 16 I
2
C Bus Interface (IIC)
Internal
SCL or
SDA
signal
REJ09B0310-0100