p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 465

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Table 16.10 Permissible SCL Rise Time (t
6. The I
IICX
0
1
and 300 ns. The I
table 16.9. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
BUFO
SCLLO
t
Indication
7.5 t
17.5 t
cyc
fails to meet the I
in high-speed mode and t
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
Standard mode
High-speed
mode
Standard mode
High-speed
mode
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
STASO
I
Specification
(Max.)
2
C Bus
in standard mode fail to satisfy the I
1000
1000
300
300
sr
) Values
Sr
φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz
/t
Sf
. Possible solutions that should be
937
←
←
←
Time Indication [ns]
Rev. 1.00 Sep. 21, 2006 Page 427 of 658
2
C bus interface specifications may
750
←
←
←
Section 16 I
2
C bus.
2
C bus interface
468
←
←
←
2
C Bus Interface (IIC)
REJ09B0310-0100
cyc
, as shown in
375
875
←
←
2
C