p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 382

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface (SCI)
Rev. 1.00 Sep. 21, 2006 Page 344 of 658
REJ09B0310-0100
Clear DR to 0 and set DDR to 1
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart
Write transmit data to TDR and
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
Clear TDRE flag to 0
set MPBT bit in SSR
All data transmitted?
End of transmission
Start transmission
Break output?
Initialization
TDRE = 1
TEND = 1
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
Note: The SMR, SCR, SCMR, and BRR
Serial transmission continuation
SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame of
1s is output, and transmission is
enabled.
SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR. Set the MPBT bit in
SSR to 0 or 1. Finally, clear the
TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
However, the TDRE flag is checked
and cleared automatically when the
DTC is initiated by a transmit data
empty interrupt (TXI) request and
writes data to TDR.
Break output at the end of serial
transmission:
To output a break in serial
transmission, set port DDR to 1, clear
DR to 0, and then clear the TE bit in
SCR to 0.
registers should not be written to
during the period from the start to the
end of transmission. This does not
apply to the processing at step [5].