p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 397

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

15.8.6
When an external clock source is used as a synchronization clock, update TDR by the DTC and
wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit
clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure
15.21).
When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC
activation source.
15.8.7
(1)
Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit
operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins
during each mode depend on the port settings, and the pins output a high-level signal after mode
cancellation. If a transition is made during data transmission, the data being transmitted will be
undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a
different transmission mode, initialize the SCI first.
Figure 15.22 shows a sample flowchart for mode transition during transmission. Figures 15.23 and
15.24 show the pin states during transmission.
Before making a transition from the transmission mode using DTC transfer to module stop,
software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting
Figure 15.21 Example of Transmission using DTC in Clocked Synchronous Mode
Transmission
Restrictions on Using DTC
SCI Operations during Mode Transitions
SCK
TDRE
Serial data
Note: * When external clock is supplied, t must be more than four clock cycles.
t
LSB
D0
D1
D2
D3
Section 15 Serial Communication Interface (SCI)
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Rev. 1.00 Sep. 21, 2006 Page 359 of 658
D5
D6
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REJ09B0310-0100