HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 148

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7. User Break Controller (UBC)
7.2.3
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets the four
break conditions.
Rev.4.00 Mar. 27, 2008 Page 104 of 882
REJ09B0108-0400
Bit
15 to 8
7
6
5
4
Bit
UBAMRH15 to
UBAMRH0
UBAMRL15 to
UBAMRL0
User Break Bus Cycle Register (UBBR)
Bit Name
—
CP1
CP0
ID1
ID0
Bit Name
UBM31 to
UBM16
UBM15 to
UBM0
Initial Value R/W
All 0
0
0
0
0
Initial Value R/W
All 0
All 0
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write
value should always be 0.
CPU Cycle/DMAC, DTC Cycle Select 1 and 0
These bits specify break conditions for CPU
cycles or DMAC/DTC cycles.
00: No user break interrupt occurs
01: Break on CPU cycles
10: Break on DTC or DMAC cycles
11: Break on both CPU and DMAC or DTC
Instruction Fetch/Data Access Select1 and 0
These bits select whether to break on
instruction fetch and/or data access cycles.
00: No user break interrupt occurs
01: Break on instruction fetch cycles
10: Break on data access cycles
11: Break on both instruction fetch and data
Description
User Break Address Mask 31 to 16
0: Corresponding UBA bit is included in the
1: Corresponding UBA bit is not included in the
User Break Address Mask 15 to 0
0: Corresponding UBA bit is included in the
1: Corresponding UBA bit is not included in the
break conditions
break conditions
break conditions
break conditions
cycles
access cycles