HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 224

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

10. Direct Memory Access Controller (DMAC)
10.4
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip
peripheral module request. Transfer can be in either the single address mode or the dual address
mode, and dual address mode can be either direct or indirect address transfer mode. The bus mode
can be either burst or cycle steal.
10.4.1
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation
register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according
to the following procedure:
1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,
2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer
3. When the specified number of transfers have been completed (when DMATCR reaches 0), the
4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is
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REJ09B0108-0400
AE = 0).
unit of data (determined by TS0 and TS1 setting). For an auto-request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus
mode.
transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent
to the CPU.
aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the
DMAOR are changed to 0.
Operation
DMA Transfer Flow