HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 549

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 14.13 Example: Flowchart of Operations in Master Receive Mode
No
No
No
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Write 0 to BBSY and SCP
Set HNDS = 0 (SCRX)
Set ACKB = 0 (ICSR)
Set WAIT = 1 (ICMR)
Set ACKB = 1 (ICSR)
Set WAIT = 0 (ICMR)
Set TRS = 0 (ICCR)
Master receive mode
Set TRS = 1 (ICCR)
Final reception?
Wait for 1 cycle
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRTR = 1?
IRIC = 1?
IRIC = 1?
(ICCR)
(Multiple Bytes Reception) (WAIT = 1)
End
Yes
Yes
Yes
No
No
Yes
Yes
[1] Set receive mode.
[2] Start receiving. Dummy read.
[3] Wait for a receive wait
[4] Determine the end of data reception.
[5] Read the receive data.
[6] Clear the IRIC flag (to cancel wait).
[7] Set acknowledge data for the final reception.
[8] Wait for TRS setting.
[9] Set TRS for stop condition issuance.
[10] Read the receive data.
[11] Clear the IRIC flag (to cancel wait).
[12] Wait for a receive wait
[13] Determine the end of data reception.
[15] Cancel wait mode. Clear the IRIC flag.
[16] Read final receive data.
[17] Issue stop condition.
[14] Clear the IRIC flag (to cancel wait).
wait for 1 byte to be received
(set IRIC at the falling edge of the 8th cycle)
or,
(set IRIC at the rising edge of the 9th cycle).
(set IRIC at the falling edge of the 8th cycle)
or,
wait for 1 byte to be received
(set IRIC at the rising edge of the 9th cycle).
(IRIC should be cleared to 0 after setting WAIT = 0)
Rev.4.00 Mar. 27, 2008 Page 505 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400