HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 565

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.4.7
The timing with which the interrupt-request flag (IRIC) is set varies according to the settings of
the WAIT bit in ICMR, FS bit in SAR, and the FSX bit in SARX. When the ICDRE and ICDRF
flags are set to 1, the level on SCL is automatically set low in synchronization with the internal
clock after the transfer of one frame of data. Figures 14.25 to 14.27 show the timing with which
IRIC is set and the control of SCL.
User processing
User processing
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
SCL
SDA
IRIC
Timing for Setting IRIC and the Control of SCL
Figure 14.25 IRIC Flag Set Timing and the Control of SCL (1)
(a) When data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
(b) When data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception
7
7
7
7
8
8
8
8
2
C bus format, no wait)
A
A
9
9
IRIC clear
IRIC clear
1
Rev.4.00 Mar. 27, 2008 Page 521 of 882
1
ICDR write (during transmission)
or ICDR read (during reception)
14. I
2
2
2
C Bus Interface (IIC) Option
REJ09B0108-0400
3
1
1
3
IRIC clear