HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 236

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HD6417144

Manufacturer Part Number
HD6417144
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 192 of 882
REJ09B0108-0400
1st, 2nd bus cycles
3rd bus cycle
4th bus cycle
Figure 10.8 Dual Address Mode and Indirect Address Operation
The SAR3 value is taken as the address, memory data is read, and the value is stored in the
temporary buffer. Since the value read at this time is used as the address, it must be 32 bits.
When external connection data bus is 16 bits, two bus cycles are required.
The value in the temporary buffer is taken as the address, and data is read from the
transfer source module to the data buffer.
The DAR3 value is taken as the address, and the value in the data buffer is written to the
transfer destination module.
Note:
Memory, transfer source, and transfer destination modules are shown here. In
practice, connection can be made anywhere if there is address space.
(When External Memory Space Is 16 Bits)
Temporary
Temporary
Temporary
DMAC
DMAC
buffer
buffer
buffer
buffer
DAR3
DAR3
SAR3
SAR3
Data
Data
DMAC
buffer
buffer
DAR3
SAR3
Data
Transfer destination
Transfer destination
Transfer destination
Transfer source
Transfer source
Transfer source
Memory
Memory
Memory
module
module
module
module
module
module

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