HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 69

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.4.2
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8
Addressing
Mode
Direct register
addressing
Indirect register
addressing
Post-increment
indirect register
addressing
Pre-decrement
indirect register
addressing
Addressing Modes
Addressing Modes and Effective Addresses
Instruction
Format
Rn
@Rn
@Rn+
@-Rn
Effective Address Calculation
The effective address is register Rn. (The operand
is the contents of register Rn.)
The effective address is the contents of register Rn.
The effective address is the contents of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rev.4.00 Mar. 27, 2008 Page 25 of 882
Rn
Rn
REJ09B0108-0400
Equation
—
Rn
Rn
(After the
instruction
executes)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
2. CPU