HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 546

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14. I
Rev.4.00 Mar. 27, 2008 Page 502 of 882
REJ09B0108-0400
Figure 14.10 Example: Flowchart of Operations in the Master Receive Mode (HNDS = 1)
2
C Bus Interface (IIC) Option
No
No
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Write 0 to BBSY and SCP
Set HNDS = 1 (SCRX)
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Master receive mode
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Final reception?
Read ICDR
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
(ICCR)
End
Yes
Yes
No
Yes
[1] Set receive mode
[2] Dummy read for starting reception (first read)
[5] Read the receive data (second and subsequent read)
[3] Wait for 1 byte of data to be received.
[4] Clear IRIC flag.
[6] Set acknowledge data for the final reception.
[7] Read the receive data. Dummy read for starting
[8] Wait for 1 byte of data to be received.
[10] Read the receive data.
[11] Set stop condition issuance. Generate stop condition.
[9] Clear IRIC flag
(Set IRIC at the rising edge of the 9th cycle of the
clock for the receive frame.)
reception when the first frame is the final receive data.