HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 265

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 11.3 CCLR0 to CCLR2 (Channels 0, 3, and 4)
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
Table 11.4 CCLR0 to CCLR2 (Channels 1 and 2)
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
Channel
0, 3, 4
Channel
1, 2
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
buffer register setting has priority, and compare match/input capture does not occur.
Bit 7
Reserved*
0
Bit 7
CCLR2
0
1
2
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture*
TCNT cleared by TGRD compare match/input
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
11.
Rev.4.00 Mar. 27, 2008 Page 221 of 882
2
2
Multi-Function Timer Pulse Unit (MTU)
1
1
1
REJ09B0108-0400