HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 569

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 14.7 Examples of Operations in which the DTC Is Used
Item
Slave address +
R/W bit
transmission/recep
tion
Dummy data read ⎯
Main unit data
transmission/recep
tion
Final frame
processing
Setting the
number of frames
of data to be
transferred in DTC
Master Transmit
Mode
DTC transmission
(ICDR write)
DTC transmission
(ICDR write)
Unnecessary
Transmission:
Number of actual
frames of data + 1
(+1 represents the
frame for slave
address + R/W
bits)
CPU reception
Master Receive
Mode
CPU transmission
(ICDR write)
CPU processing
(ICDR read)
DTC reception
(ICDR read)
(ICDR read)
Reception:
Number of actual
frames of data
Rev.4.00 Mar. 27, 2008 Page 525 of 882
Slave Transmit
Mode
CPU reception
(ICDR read)
⎯
DTC transmission
(ICDR write)
Unnecessary
Transmission:
Number of actual
frames of data
14. I
2
C Bus Interface (IIC) Option
Slave Receive
Mode
CPU reception
(ICDR read)
⎯
DTC reception
(ICDR read)
CPU reception
(ICDR read)
Reception:
Number of actual
frames of data
REJ09B0108-0400