HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 581

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12. Points for caution when reading ICDR and accessing ICCR in slave transmit mode
TRS bit
SDA
SCL
Figure 14.34 Timing for Reading ICDR and Accessing ICCR in Slave Transmit Mode
In I
during the period shaded in figure 14.34. However, in interrupt handling processing that is
generated in synchronization with the rising edge of the 9th cycle of the clock, reading ICDR
or reading/writing to ICCR causes no error because the shaded period has passed before
making the transition to interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
⎯ Before starting the receive operation of the next slave address, finish the read of ICDR data
⎯ Monitor the BC2 to BC0 counter in ICMR; when the count is 000 (8th or 9th cycle of the
2
that has been received so far or the read/write of ICCR.
clock), wait for at least two transfer clocks to let the shaded period pass. Then, read ICDR
or read/write to ICCR.
C bus interface slave transmit mode, do not read ICDR or do not read/write to ICCR
Address reception
R/W
8
Detection of rise of 9th transmit/receive clock
Period in which read from ICDR and read from
or write to ICCR are prohibited
A
9
(6 peripheral clocks)
Erroneous waveforms
Rev.4.00 Mar. 27, 2008 Page 537 of 882
14. I
2
C Bus Interface (IIC) Option
Write to ICDR
REJ09B0108-0400
Data transmission
Bit 7