HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 491

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.6.4
Figure 13.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
or output, starts receiving data, and stores the received data in RSR.
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Synchroniza-
tion clock
Serial data
RDRF
ORER
Serial Data Reception (Clocked Synchronous Mode)
Figure 13.18 Example of SCI Operation in Reception
RXI interrupt
request
generated
Bit 7
Bit 0
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
1 frame
Bit 7
Bit 0
RXI interrupt
request
generated
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 447 of 882
Bit 1
Bit 6
ERI interrupt
request generated
by overrun error
Bit 7
REJ09B0108-0400